EMC as an external storage interface makes it possible for MCUs to pursue high capacity and high speed. As a relatively common external memory chip SDRAM, its relatively complex data transmission timing, after the emergence of EMC, there will be problems, talk about the things between them today.
The NPC1788 chip from NXP has a controller that controls external storage. It is a multi-port storage peripheral that supports asynchronous static storage devices such as RAM, ROM and Flash, as well as single data rate transmission. SDRAM is such a dynamic memory. The controller has 26 address lines and 32 data lines. It supports 4 static memory chip select address mappings and 4 dynamic memory chip select address mappings. The figure below shows the location of the EMC interface in memory mapping.
When the EMC is connected to an external dynamic memory, the occupied address lines are relatively small, which is related to the storage structure of the dynamic memory. Take SDRAM, the internal storage is distributed in rows and columns, as shown in the following figure, like the table, there is a corresponding row address and column address, each small square is a storage unit. When addressing it, it is necessary to first perform row address addressing and then column address addressing to select the determined operating unit. Therefore, its row and column address lines can be time-multiplexed, which also determines that it occupies fewer address lines.
â—† EMC provides pin-compatible signal transmission for dynamic memory.
EMC_D[31:0]: data line;
EMC_A[14:0]: address line;
EMC_CLK: clocks the SDRAM;
EMC_CKE: Clock enable bit of SDRAM;
EMC_DQM[3:0]: data mask signal;
EMC_RAS: SDRAM row address strobe signal;
EMC_CAS: SDRAM column address strobe signal
EMC_DYCS[3:0]: chip select signal of SDRAM;
EMC_WE: SDRAM write enable.
When the pins of the dynamic memory device are connected to the EMC, the EMC registers need to be configured. It can be seen that for SDRAM, there are a lot of registers for the time parameter configuration, which need to be configured according to the actual connected external storage device. Of course, these time parameters can be found in the data sheet of the external storage device.
But we can't take it lightly. Some wrong time configuration may lead to data transfer failure, which may cause data loss inside dynamic memory. For dynamic memory devices, it requires constant refresh to save data. This is an important operation, so the configuration of the refresh time is very important. For the commonly used SDRAM chip IS42S16400, find the time parameter in the data sheet below, which means that the time required to refresh 4096 times is 64ms, that is, the time to refresh once is 15.625us, if refreshed If the period is larger than this, SDRAM cannot save the data. For the LPC1788 EMC module, it has such a time parameter register EMCDynamicRefresh, which can be used to set the SDRAM refresh time.
Since the register is based on the EMC clock, the setting of this refresh time is also related to the EMC clock. During the configuration process, it is calculated according to the current clock to avoid errors. For connecting multiple dynamic external memory chips, they share this refresh time. In this case, according to the refresh cycle required in each data sheet, the shortest time for each refresh time is required. The refresh is completed within the specified time. At the same time, in the case of supporting thermal reset, it should also be noted that since the EMC clock changes during the thermal reset, the refresh cycle will change at this time. In the configuration process, the above situation should also be considered.
For other time parameters, the correct configuration can be done against the EMC configuration of the time parameter configuration and the corresponding external memory chip data sheet. When the EMC configuration is completed, the external memory can be accessed by accessing the bus address.
This and external storage data transmission method implemented by EMC will be more and more widely used in future embedded products, which provides a new opportunity for small-capacity MCUs.
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