1 deep submicron BiCMOS [B] technology
The device enters the deep submicron feature size. In order to suppress the MOS through current and reduce the short channel effect, the deep submicron manufacturing process places the following strict requirements:
(1) High quality gate oxide film. After the thickness of the gate oxide film is thinned proportionally, a low defect density, a good anti-impurity diffusion, a low interface state density and a fixed charge Si/SiO2 interface are required.
(2) Controllable and repeatable channel doping. The adjustment threshold voltage is reached and the punchthrough is suppressed.
(3) The source and drain junctions are shallower. Highly doped regions have good lattice integrity.
(4) Excellent PN structure. High surface concentration, low contact sheet resistance and low junction leakage current.
(5) Fine LDD structure. The heavily doped N+ or P+ implanted impurity does not laterally diffuse under the gate, increasing the source-drain punch-through voltage and reducing the hot carrier injection introduced by the high electric field.
In addition, a high-quality P-type epitaxial film with a thickness of 1 to 2 μm is grown on the heavily doped silicon substrate P+-Si <100> to obtain a stable and repeatable surface, and the wafer has a uniform film thickness and precision. Doped epitaxial film, excellent lattice integrity, meets the requirements of deep sub-micron integrated circuits for silicon lining materials.
An epitaxial layer is deposited on a silicon substrate having a BLN+ buried layer. The thickness is determined by the upward diffusion of the vertical NPN tube buried layer [1], which determines the distance between the silicon surface and the BLN+ buried layer. The change in the thickness of the epitaxial layer directly reflects the change in distance. The device parameters are affected by the thickness of the epitaxial layer: bipolar BUCEO and BUCES, collector series resistance, Early voltage, fast response voltage of NMOS, breakdown voltage BUDS of NMOS and PMOS, these parameters increase with the increase of epitaxial thickness Big. The doping concentration of the epitaxial layer is determined by the lateral device. When the doping concentration increases, BUnpn, BUpnp, and BUSDP both decrease. Therefore, an epitaxial layer of suitable resistivity is selected. Its doping concentration makes the bipolar and CMOS parameters meet the circuit requirements.
In this paper, in order to visually show the bipolar-type deep sub-micron BiCMOS[B] structure compatible with Twin-Well CMOS devices, the chip structure technology [2-4] is used to obtain the chip profile structure, and the computer and its provided The software, which depicts a schematic representation of the changes in the formation process and structure of the chip surface, internal devices, and interconnects in the process.
2 chip profile structure
The chip structure technology [1-3], using the computer and the software it provides, can obtain the typical cross-sectional structure of the deep submicron BiCMOS [B] chip. First, the designer finds various typical components in the circuit: PMOS, NMOS, NPN (longitudinal), PNP (longitudinal), Poly resistance, and PNP (transverse). Then the manufacturing personnel will carry out the sectional structure design of these components, select the appropriate size and different markings of each layer of the sectional structure, and indicate the level after the completion of each process in the process, and design the component structures that can be spliced ​​well with each other. (or selected in the component structure library), as shown in Figure 1 [A], [B], [C], [D], [E], and [F], etc. (Do not treat them as connected together) ). Finally, the structure of each component is arranged and spliced ​​in a certain way to form a chip cross-sectional structure, as shown in Figure 1-1A. Based on this structure, the Cf field capacitance and the Poly resistance are introduced to obtain the structure shown in Figure 1-1B. If a single or multiple component structure other than that in Figure 1-1 is introduced or a change is made to the component structure, a variety of different structures can be obtained. Choose a structure that is associated with the design circuit. This article only covers Figure 1-A technology.
The parameters in Table 1 are: P-type epitaxial layer thickness is TP-EPI, deep phosphorus area (DN) junction depth/sheet resistance is XjDN/RSDN, NP junction depth/sheet resistance is XjN+/RSN+, P+ junction depth/ The sheet resistance is XjP+/RSP+, the base junction depth/sheet resistance is XjPb/RSPb, and the buried junction depth/sheet resistance is XjBL/RSBL. Other parameter symbols are the same as usual.
3 Process Technology
The circuit uses 0.25 μm (CMOS) / 1 ~ 2 μm (bipolar) design rules, using deep sub-micron BiCMOS [B] manufacturing technology. Table 1 shows the main components, manufacturing techniques and main parameters of the circuit. It is based on a bipolar process and the components it produces, and changes the chip structure and manufacturing process to produce a compatible technology for Twin-Well CMOS devices, which ultimately forms on the same silicon substrate. The main components in the IC shown in the table are interconnected. The circuit or layers are transformed into IC chips of reduced planar and cross-sectional structures. If the various parameters obtained in the table reach the specification value and are suitable for the requirements of the designed circuit, the function and electrical performance of the circuit chip can reach the design index.
In order to realize the deep sub-meter BiCMOS [B] technology, the bipolar manufacturing process is changed as follows.
(1) After the formation of the BLN+ buried layer, the BLP+ buried layer and the P-type thin layer epitaxy, 11B+ and 31P+ are implanted and advanced to form a reverse Twin-Well which is connected to the buried layer to form a bipolar isolation. Introducing field implants, silicon is locally oxidized to form CMOS isolation.
(2) After the base region is advanced, anti-punch-through and channel implant, gate oxide and etch buried vias (one of the bipolar E-region processes), and Poly deposition and light doping are introduced to form deep sub-micron CMOS. Silicon gate, NLDD/PLDD implantation, Si3N4 deposition, etching to form sidewall structures.
(3) 75As+ and low energy 11B+ implant, respectively, to generate N+SN- and P+SP- regions, and to sputter Ti to form TiSi2/N+SN-region, TiSi2/P+SP- region, E(N+Poly or P+Poly diffusion forms an EN+ region or an EP+ region)/C doped region and a base region are simultaneously contacted to form a source/drain doping region. The introduction of these basic processes described above has resulted in significant changes in both bipolar chip structures and processes. After the process is completed, PMOS [A] and NMOS [B] and vertical NPN [C] and vertical PNP [D] as well as Poly resistance [E] and lateral PNP [F] are fabricated, and deep sub-meter BiCMOS [B] is used. To represent.
The schematic diagram of the chip cross-section after the process is completed is shown in Figure 1. Compared with the submicron BiCMOS [B] [4], the main difference is: (1) P-epi / P + - Si <100> is used as the silicon substrate. (2) Reverse double well. (3) The gate feature size is 0.25 μm. (4) Use TiSi2 and tungsten plug. (5) The N-type and P-type doped Poly diffusion is used to form the emitter region.
The electrical performance/qualification rate of the deep sub-meter BiCMOS [B] circuit is closely related to the manufacturing of various parameters, and the basic parameters for chip manufacturing are determined, as shown in Table 1. In the chip manufacturing process, on the one hand, it is necessary to ensure that the process parameters and electrical parameters reach the specification value. On the other hand, in the mass production, the circuit must have high yield, high performance and high reliability. According to the electrical characteristics of the circuit, various parameters are proposed: (1) process parameters, (2) electrical parameters, and (3) silicon substrate resistivity / epitaxial layer thickness and resistivity. To this end, in the chip manufacturing process, the process consisting of each step is realized, and the specific process conditions of each process are determined to ensure that the required specification values ​​of various parameters are achieved.
The mask used in each photolithography process in the process can be seen from the cross-sectional structure of the process section below, and 21 lithography is required. Alignment exposure is the most critical process in the lithography process. Since 21 lithography is required, for lithography, high graphics resolution is required, and good graphics registration accuracy is required. The lithographic alignment exposure is strictly aligned, registered, and within a defined error.
4 Process
The basic processes identified by the process specification, interrelated, and combined in a certain order form the process of the deep submicron BiCMOS [B] chip structure shown in FIG. In order to realize this process, the basic processes of (1) to (3) above are introduced in the bipolar process, which not only increases the manufacturing process, but also increases the technical difficulty, which makes the chip structure change significantly and changes its process. Thus, a deep submicron BiCMOS [B] process is realized.
The chip process is constituted by various basic processes such as multiple oxidation, photolithography, impurity diffusion, ion implantation, thin film deposition, and sputtering of metal. These procedures provide:
(1) Forming various components in the circuit chip: NMOS, PMOS, Poly resistance, NPN (longitudinal), PNP (lateral), PNP (longitudinal), and the like.
(2) Impurity layers in silicon that are precisely controlled by these circuit components: BLN+, BLP+, P-EPI, DN, ret.TW, PF, NF, Pb, Nb, channel doping, TiSi2/N+ SN-, TiSi2/P+SP-, TiSi2/N+Poly, TiSi2/P+Poly, TiSi2/EN+, TiSi2/EP+, and the like.
(3) The dielectric layers required to form an integrated circuit: F-Ox, G-Ox, TEOS, BPSG, Si3N4, and the like.
(4) These circuit components are connected to form a metal layer AlCu, W Plug required for the integrated circuit. These manufacturing steps that must be performed in a given order constitute the process.
By using a computer, the processes of the chips can be obtained by connecting the processes to each other in accordance with the order of the processes in the chip manufacturing process. The process consists of various processes, and the process is composed of various steps. According to the electrical characteristics of the design circuit, the process specification number and process number are selected to obtain the required process and electrical parameters.
Using the chip structure technology [1-3], the cross-sectional structure is obtained, and the structure corresponding to each process profile is obtained by using a computer and software provided thereby, thereby obtaining various processes of chip fabrication. The chip process consists of the above various processes to determine the deep submicron BiCMOS [B] process profile structure, as shown in Figure 2. According to each process in the process, it can be drawn to reflect the corresponding planar structure after each photolithography development or etching. The chip structure after each process plane/profile structure or process can visually show the changes in the formation process and structure of the chip surface, internal components, and interconnections in the process.
(1) Substrate material P-epi/P+Si <100>, initial oxidation (Init-Ox), photolithography BLN+ buried layer, corrosion SiO2, BLN+ region oxidation (BLN+-Ox), 121Sb+ implantation, as shown in Fig. 2 1 is shown.
(2) Injection annealing, BLN+ region advancement/oxidation (BLN+-Ox), photolithography BLP+embedded layer, corrosion SiO2, BLP+ region oxidation (BLP+-Ox), 11B+ implantation, as shown in Figure 2-2.
(3) Injection annealing, BLN+/BLP+ buried layer propulsion, etching net SiO2, P-type thin layer epitaxy (P-EPI), pre-oxidation (Pre-Ox), lithography ret.NW, 31P+ implantation, corrosion and residual SiO2 , as shown in Figure 2-3.
(4) Photolithography ret.PW, 11B+ implantation, etching and residual SiO2, as shown in Figure 2-4.
(5) Injection annealing, ret.NW/ret.PW propulsion/oxidation, photolithographic DN region, 31P+ implantation, etching and residual SiO2, as shown in Figure 2-5.
(6) Injection annealing, DN zone advancement/oxidation, etching of SiO2, substrate oxidation (Pad-Ox), Poly/Si3N4 deposition, photolithographic source region, etching Si3N4/Poly, as shown in Figure 2-6.
(7) Lithography P field area, APT. (anti-punch) 11B+ deep injection, 11B+ shallow injection, as shown in Figure 2-7.
(8) Photolithography N field region, 75As+ implant, as shown in Figure 2-8.
(9) Injection annealing, field oxidation (F-Ox), lithography Pb base region, etching Si3N4/Poly, 11B+ implantation, as shown in Figure 2-9.
(10) Photolithography Nb base region, etching Si3N4/Poly, 31P+ implant, as shown in Figure 2-10.
(11) injection annealing, Pb/Nb base promotion/oxidation, four layers (SiON/Si3N4/Poly/SiO2) etching, pre-gate oxidation, photolithography N-channel region, APT.11B+ deep implant, 49BF2+ shallow implant, eg Figure 2-11 shows.
(12) Photolithography P channel region, APT.75As+ deep implant, 75As+ shallow implant, as shown in Figure 2-12.
(13) Etching the pre-gate oxide layer, implant annealing, gate oxide (G-Ox), photolithographic buried via (emitter region), and etching SiO2, as shown in Figure 2-13.
(14) Poly deposition, Poly resistance 75As+ implantation, injection annealing, lithography Poly, etching Poly/SiO2, as shown in Figure 2-14.
(15) Source/drain oxidation (S/D-Ox), photolithographic NLDD region, 75As+ implant (Poly implant not shown), as shown in Figure 2-15.
(16) Lithographic PLDD region, 49BF2+ implant (Poly implant not shown), as shown in Figure 2-16.
(17) Injection annealing, forming SN-, SP-region, Si3N4 deposition, etching to form Si3N4 spacer, source/drain oxidation (S/D-Ox), as shown in Figure 2-17.
(18) Lithographic N+ region, 75As+ implant (Poly implant not shown), etches SiO2, as shown in Figure 2-18.
(19) Lithographic P+ region, low energy 11B+ implant (Poly implant is not labeled), etches SiO2, as shown in Figure 2-19.
(20) Injection annealing to form EN+, EP+, N+SN-, P+SP-, N+, P+ regions (not labeled SN-, SP-), sputtering Ti, RAT annealing (1)/(2 ), TiSi2, TEOS/BPSG deposition/densification is formed, as shown in Figure 2-20.
(21) Photolithographic contact holes, etching BPSG/TEOS, as shown in Figure 2-21.
(22) Sputtering Ti/TiN, RTA N2 annealing, CVD W deposition, etching W/TiN/Ti, sputtering metal (metal), photolithography metal, etching TiN/AlCu, as shown in Figure 2-22 .
It can be seen from the deep submicron BiCMOS [B] process and cross-sectional structure that PMOS, vertical NPN, and lateral PNP are all fabricated in N-Well, and both NMOS and vertical PNP are formed in P-Well. The main features of the process are as follows.
(1) The reverse double well region is formed by diffusing N and P type impurities into the P-epi/P+ type substrate grown P-type epitaxial layer, and forms isolation, that is, Twin-Well is connected to BLN+ and BLP+.
(2) P+ doping of the NPN base region (Pb) contact and the emitter region of the PNP (transverse bipolar type) At the same time, the source region and the drain region are formed in the N-Well to produce a PMOS.
(3) Contact N+ doping of the NPN collector region and the PNP base region (longitudinal bipolar type) At the same time, the source region and the drain region are formed in the P-Well to produce an NMOS.
(4) In order to obtain a low saturation voltage drop at a large current, a deep-diffusion diffusion of a high concentration collector is used to form a deep phosphorus region (DN) which is in contact with the BLN+ buried layer.
(5) Using N+Poly as the NPN polysilicon emitter to form an EN+ shallow junction and a small emitter. The doped out-diffusion of Poly arsenic in the shallow Pb base region forms the emitter region of the NPN, resulting in a high cutoff frequency of the bipolar transistor. Similarly, P+Poly is used as the PNP polysilicon emitter to form EP+ shallow junctions and small emitters.
5 Conclusion
Twenty-one masks were used in the process, and each lithography determined the planar structure and lateral dimensions of each layer of the deep submicron BiCMOS [B] chip. After the process is completed, the planar structure and lateral dimensions, cross-sectional structure and longitudinal dimension of the layers of the chip, impurity concentration, distribution and junction depth in silicon, circuit function and electrical performance are determined. The structure of the chip and its size and the concentration of impurities in the silicon and their junction depth are the key to the process. They are not only related to the following parameters of the bipolar type.
(1) Silicon substrate material resistivity, P-type thin epitaxial layer resistivity and thickness TP-EPI.
(2) BLN+, BLP+ buried junction depth XjBLN+/XjBLP+ and its thin layer resistance RSBLN+/RSBLP+.
(3) Pb/Nb base width XjPb/XjNb and its sheet resistance RSPb/RSNb.
(4) N+Poly/EN+, P+Poly/EP+ emitter junction depth XjEN+/XjEP+ and its sheet resistance RSEN+/RSEP+.
(5) The deep phosphorus region DN junction depth XjDN connected to the buried layer and its sheet resistance RSDN.
(6) Device breakdown voltage BUCEO/BUCBO, amplification factor β, and cutoff frequency f TP.
Also, it is related to the following CMOS parameters.
(1) Silicon substrate material resistivity, P-type thin epitaxial layer resistivity and thickness TP-EPI.
(2) ret. N-Well, ret. P-Well well depth Xjret.NW/Xjret. PW and its sheet resistance Rjret.NW/RSret.PW.
(3) Each dielectric layer and gate oxide layer thickness TF-Ox/TTEOS/TSi3N4/TG-Ox.
(4) N-Poly resistance.
(5) Effective channel length.
(6) N+SN-, P+SP- source-drain junction depth XjN+/XjP+ and its sheet resistance RSN+/RSP+.
(7) Device threshold voltages UTN/UTP, UTFN/UTFP, source-drain breakdown voltage BUDSN/BUDSP and transconductance, etc., as shown in Table 1.
In addition, the bipolar and CMOS parameters must be traded off and optimized to match each other.
The latch-up phenomenon of CMOS circuits usually occurs by the presence of a parasitic PNP and a NPN thyristor formed by a CMOS well structure.
If any of the source/drain junctions are instantaneously forward biased (eg, spurious noise, voltage overshoot, electrostatic discharge, or a trigger applied by a signal level input before the power is turned off), then positive feedback is caused because of the set of one transistor The electrode is fed to the base of another transistor and vice versa. This causes a sustained high current flow between the USS and the UDD, resulting in a latch-up condition.
In order to suppress latch-up, in addition to using heavily doped substrates, methods that can be employed include the use of reverse wells to reduce well resistance and effectively reduce vertical PNP and lateral NPN device gain. Thereby, high energy ion implantation forms a reverse well.
After the process is completed, the wafer PCM (process and electrical parameters in Table 1) data is tested to meet the specification values ​​before the chip electrical characteristics can be tested.
references
[1] Pan Guizhong, Jiang Peicheng, Ren Qi, Zhao Pengnian. MB12 LSI for S1240[J]. Microelectronics and Computer, 1998(02).
[2] Pan Guizhong. Analysis of CMOS chip structure and manufacturing technology [J], Integrated Circuit Applications, 2017, 34(4).
[3] Pan Guizhong. MOS Integrated Circuit Structure and Manufacturing Technology [M]. Shanghai Science and Technology Press, 2010-01.
[4] Pan Guizhong. MOS Integrated Circuit Process and Manufacturing Technology [M]. Shanghai Science and Technology Press, 2012-06.
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