Simulation Technology for Small Signal Output Impedance

Measure the output impedance of a cascode, directly add DC voltage source AC=1 at the source, then let the direct AC simulation, and finally divide the voltage by the current to get the output impedance. All circuits that require Rout can also be implemented by adding vcvs to get its output impedance.

A few days ago I saw my previous design error budget, which has specific requirements for Rout and the maximum value of mismatch. As soon as I thought about the design review I was about to face, I immediately screamed and ran away and simulated.

(a) Rout

A simple cascode (or everything that requires Rout), how do you get its output impedance?

First throw a cadence schemaTIc:

Simulation Technology for Small Signal Output Impedance

(Sorry! In order to be able to plot the current, I put a lot of vdc with dc=0, such as V4, V5, V7..... I don't know why the current of those transistors directly plot can't... If everyone has a good Method, please be advised!)

VDD = 1.2V. The top two rows of pmos are divided by two fixed voltage sources.

Because my cascode is brought to bias BJT, so the first two roads are all BJT (why should put two the same branch? That... because I still have mismatch to run). The far right side is a bit special.

The bottom rightmost is a vcvs (or the libraray inside the analogLib). The reason why there is no direct addition of BJT is that BJT's equivalent resistance destroys the branch of cascode Rout. Therefore, I only used vcvs as a fixed DC bias voltage. (In fact, think again, it is ok to use BJT directly. The key is the ideal inductor above. The larger the value, the better.) I didn't think too much at the time, so I used my own vcvs...

Solving small signals requires running AC simulaTIon, V=I*R, R=V/I

For the sake of simplicity, I added idc to the far right. The DC of this idc is 0, but AC is 1. Therefore, the Rout I need to get is directly the AC voltage of the line that is highlighted.

Well, let's run an AC to see it!

Simulation Technology for Small Signal Output Impedance

Huh! It looks like an AC curve of opamp!

When DC, there is actually 32.8341GV, that is, Rout is 32.8341GOhm. Wow! Really big!

Compare the results of the hand calculation: the gds of P2 is 2.386n, the gm of P3 is 2.972u, and the gds is 45.06n, so the rough calculation, the Rout of DC should be gm3/(gds2*gds3), which is 27.64GOhm.

Well, in general, the difference is not very big, after all, the actual formula is not so rough!

Then, because my circuit works, there will be a 100KHz sampling clock, I will specifically mark the value of 100KHz, which is 1.8836GOhm.

After that, I used to toss myself and changed the W and L of P3. It was just 1u/500n, I changed it to 2u/1u, then ran it again and got new results:

Simulation Technology for Small Signal Output Impedance

The gds of P2 change little, the gm of P3 is 2.918u, and the gds is 12.32n.

Comparing the above results, the most significant change is gds3, which is significantly smaller. Therefore, the Rout of DC has also become 96.4683 GOhm.

Well, it’s expected! Short channel effect.

and many more! How is it getting smaller at 100KHz? From 1.8836 GOhm to 1.18324 GOhm... This is too...

The parasitic cap is increased, so the frequency of the fall is advanced. It seems that if the structure is the same, if you want a large DC gain, you still have to pay some extra cost!

In order to verify their own ideas, the author continued to adjust P3 to 4u/2u and got the following waveform:

Simulation Technology for Small Signal Output Impedance

Unsurprisingly, DC's Rout has also grown to 152.915 GOhm. The Rout corresponding to 100KHz also became smaller at 573.243 MOhm.

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