Printed circuit board design process includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process, no matter which process is found, you must return to the previous process and reconfirm or correct it.
Preparation before layout:
1 Check if the capture point setting is correct. The 08 process is 0.1, the 06 process is 0.05, and the 05 process is 0.025.
2 Cell name cannot start with a number. Otherwise, DRACULA check cannot be done.
3 Consider the direction and location of the PIN before layout
4 Before the layout analysis circuit, complete the same function MOS tube drawn together
5 Pre-order the two layers of metal. The orientation of the grid in a figure is as uniform as possible, and there should be no horizontal and vertical.
6 For pin classification, vdd, vddx, please be careful not to confuse, the n wells with different potentials (substrate connected to different voltages) are separated. The circuit of mixed signal pays special attention to this point.
7 Open icfb in the correct path (usually to ~/opus).
8 When changing the cell, check the path, be sure to change it under the correct library, in case the copy-over cell is changed under other libraries.
9 Find the N wells of different potentials.
Note when laying out:
10 Remember to check and save after changing the schematic
11 Return to the origin after completing each cell
12 The number of DEVICEs is the same as in the schematic diagram (when there are pipes in parallel); whether the size of each DEVICE is the same as the schematic. Generally, after getting the schematic diagram, there will be a rough plan for the layout. First draw DEVICE, (the DIVECE does not have to use the minimum spacing, and consider the connection space to leave a gap according to experience) and then connect. After drawing DEVICE, look at the parameter check right or wrong from EXTRACTED. The direction from which each end of each device device is connected to other objects must be considered (related to the level of experience and floorplan).
13 If a cell calls another cell, the vssx, vddx, vssb, and vddb of the called cell should be labeled with PIN if they are not connected to the outer cell. Otherwise, the diva check is passed. Try to connect the lower layer cells as much as possible.
14 Try to pick up the PIN with the topmost metal.
15 Pull out the line and pull it to the edge of the cell. Remember to leave the space for layout.
16 metal wiring should not be too long;
17 Capacitors are generally drawn at the end and are pieced together in the gap.
18 small size mos tube holes can be played a little less.
Do not use the y0 layer when the LABEL identifies the component. The mapfile does not recognize it.
20 Do not try to trace the channel on the tube; the effect of M2 is smaller than M1.
21 The voltage of the upper and lower plates of the capacitor should be evenly distributed; the length and width of the capacitor should not be too large. Multiple resistors can be connected in parallel.
22 Polysilicon gates cannot be perforated to connect metal at both ends.
23 The hole in the grid is preferably placed in the middle of the grid.
The 24 U-shaped mos tube covers the diff layer with a square grid. Do not use the layer generation method to generate a U-shaped grid.
25 generally punch at least two
26 Contact area allows, the more you can play, the better, especially the input/output part, because the current is larger. But if the contact resistance is much larger than the diffusion, it is not applicable. The wider the conductive line, the better, because the resistance value can be reduced. But also increased the capacitance value.
27 Does the thin oxide layer have a corresponding implant layer?
28 metal connection holes can be embedded in the middle of the diffusion hole.
29 Note where the two metal joints overlap. Note the minimum width of the metal wire.
30 Wiring joints must be overlapped, and zooming in on this area can avoid this error.
31 When placing small CELLs, be careful not to squeeze too close, leaving no room for wiring. The last line can only be crossed over from the DEVICE.
32 Text2, y0 layer is only used for inspection or marking, not for lithography manufacturing.
33 The power cable/ground cable inside the chip is separated from the power cable/ground cable on the ESD; the power cable/ground cable of the digital-to-analog signal is separated.
The size of the 34 Pad's pass window is drawn as an integer 90um.
35 The line connecting the Esd circuit cannot be broken. If you change the direction, do not change the metal layer.
36 Esd circuit without VDDX, VSSX, is VDDB, VSSB.
37 PAD and ESD are best connected with M1, the width is not less than 20um; when using M2 connection, the VIA hole is not used on the pad, and it is played on the ESD circuit.
38 The connection between the PAD and the chip's internal cell is taken over from the ESD circuit.
39 The SOURCE of the Esd circuit is placed on both sides, and DRAIN is placed in the middle.
40 ESD's D-end hole to poly spacing is 4, S-end to poly spacing is ^ + 0.2. Prevent large current from entering the D-end when affecting poly.
41 ESD pmos tubes are at least 70um apart from other ESD or POWER nmos tubes.
42 large size pmos/nmos and other nmos/pmos (non-powermos and ESD) are not enough distance 70um, but it is best not to be less than 50um, add NWELL in the middle, put NTAP.
43 What is the difference between the isolation effect of NWELL and PTAP? NWELL is deeper and the effect is better.
44 Only the tubes in the esd circuit can use 2*2um holes. How to judge the ESD circuit? The D/G of the pull-up P tube is connected to VDD, and the S is connected to the PAD; the G/S of the pull-down N tube is connected to the VSS, and the D is connected to the PAD.P/N tube to function as a diode.
45 When the ESD is placed, nmos is placed at the outermost edge, pmos.
46 Regarding the matching circuit, the amplifying circuit does not need to match the current source below. What is a match? Make the lithography environment in which the tubes that need to be matched are located. Matches are divided into horizontal, vertical, and center matching.
1221 is vertical matching, 12 is center matching (when upper 1 is turned to lower 1 and upper 2 is also lower 2)
twenty one
The center matches best.
47 The matching pipe with very small size is not strict with the matching drawing method. More than 4 matching pipes, the matching method of partial and overall matching is the best.
48 Draw a dummy on the left and right sides of the mos tube of the matching circuit. The size of the polygon is the same as the tube size. The distance between the dummy and the adjacent first poly gate is equal to the spacing between the poly gates.
49 resistor matching, such as 1, 2 two resistors need to match, still 1221 and other methods. The resistor dummy is grounded at both ends vssx.
Do not hit 50 Via on the resistor body or on the edge of the capacitor (poly).
51 05 process resistor layer is only for inspection
52 The more holes in the resistance connection, the resistance of each VIA hole is parallel, and the resistance formed by the hole becomes smaller.
53 The dummy of the resistor is guaranteed to be at the edge of the same resistance as other resistors.
54 Capacitance matching, value, wiring, position matching.
55 The connection of the pad connecting the fuse to the fuse is slightly wider, because the current passing through is larger. The fuse of the fuse is made of the uppermost metal.
56 About powermos
1 powermos is generally connected to the pin, to be connected with a wide enough metal wire,
2 Several ways to reduce the area.
3 grid spacing? no request. The length of the grid cannot exceed 100um
57 Power mos should consider the case of instantaneous large current passing, ensuring that the resistance of the path through which the current reaches each other is not much different (according to all cases where large current passes).
58 The metal layer dummy should be in line with the metal, that is, if M2 is traversed, the dummy of M2 is also horizontally oriented.
59 The pin, label, etc. of the low-level cell should be neat, and should not be deleted for later use.
If the grid of the matching circuit is traversed, the metal wire used for the connection will be vertical and the metal layer will be aligned with the specified metal.
61 Effects of metal connections of different widths? The impact of the entire layout area is large and can be ignored.
62 output terminal capacitance should be small. Multiple tubes are connected in parallel, and one end is output to pay attention to this.
63 When doing DRACULA check, if you run drc first, do lvs check when drc check is not finished, then each step of drc check will be faster than each step of lvs check; otherwise, lvs will be faster than drc.
64 After the final DRACULA is passed, add ptap to the gap in the layout diagram. Fill the gap with thin-oxid first, and then punch the hole. The metal width should not exceed 10, that is, a row of up to 8 holes (06 process)
65 To prevent signal crosstalk, add PTAP between the two circuits. This PTAP is connected to the VSS PAD separately.
66 When the voltage on the metal is very large, in order to avoid sharp angle discharge, the corner is inclined, and can not take a right angle of 90 degrees.
67 If w=20, draw two w=10mos tubes in parallel
68 The common end of the parallel tube is the S end, or the D end; the common end of the tube in series is the s/d end.
Error check:
69 Is there a connection at each end of the DEVICE; the connection is correct;
70 When completing the layout check, check whether there is a connection in each wiring. Pay special attention to VSSX, VDDX.
71 Use the SHOTS to highlight the line when checking the line, so that you can find the wire that can be combined or shortened.
More than 72 resistors (greater than two) are labeled DUMMY. Ensure that each resistor is in the same environment as the lithography. The outermost resistor has an NPIM layer that exceeds EPOLY2 by 0.55 um, which is half the pitch of the two resistors.
73 Unrelated MOS tube THIN should be disconnected, do not connect together
74 Parallel pipes pay attention to the leakage source merge, do not connect the wrong line. The source end of one tube is also the source end of another tube
75 The name of the uppermost pin when doing DRAC check is identified by text2. The name of Text2 should be the same as the name of the pin.
76 big CELL do not do DIVA inspection, use DRACULE.
77 Text2 layer should be in the topmost cell. If you hit the PAD and call this PAD at the top level, Dracula can't recognize the pin.
78 Eliminate the lvs error of the resistor dummy, remove the nimp and RPdummy layers from the edge of the resistor, do not cover the dummy
79 06 The minimum width of M1 in the process is 0.8. If the M1 line is 0.8, although the div's drc is not given an error, the DRACULE's drc will report an error at the corner. To widen the metal line at the corner.
80 Finally, DRACULA's lvs passed, but drc has not passed. Every time you correct the drc error, you can save the layout map as layout1, and then correct it. So as not to affect the lvs, the old version is saved.
The connection between the 81 cells should be connected in the lower layer cell as much as possible. Do not connect it in the upper cell. Do not connect it in the highest cell. Because the layout of the highest cell is often changed, the routing is easy because the cell moves. confusion.
82 DRACULA's drc can't check that the pad must meet the rule that the pad is not related to the pad.
83 Do two windows when doing DRACULA check, one for lvs and one for drc. Can be done at the same time, saving time.
Easy mistake
84 resistance forget to add dummy
85 After the NS function is used, there is no restoration (select AS), and then the whole image is moved. As a result, the components of the NS are not moved and the graphics are destroyed.
86 When using the strech function, select it incorrectly. Pay attention to the bottom left corner of the figure for each operation.
The substrate of the input amplifier tube in the 87 Op circuit is not connected to vddb/vddx.
88 Is it done after pressing the capslock button without restoring?
Way to save area
89 The power cord can be drawn below the device. Save area.
90 resistors can be routed above, and the area where the resistors are drawn can be fully utilized.
91 The longer the length of the resistor is, the more space is saved.
92 When the wire is routed, the width of the wire is minimized to save the area. The width of the hole is not required.
93 When making a new version of the layout diagram, the old map is saved and should not be changed or deleted. If the line of the lower layer CELL is connected to the outer layer CELL when reducing the area, you can start from changing the connection and reduce the area of ​​the line.
The area in the 94 layout is divided by the interval of the device, device, and the space of the trace. Reduce the area generally starting from the wiring space, change FLOORPLAN
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