The space age not only promoted the launch vehicle technology, but also applied the rapid development of satellite technology and deep space exploration technology, and also enabled the ground-based Internet to develop into a space-based space network, extending to 120 million kilometers of Mars, promoting space-based embedding. The rapid development of aerospace microelectronics application technologies such as image processing technology.
Embedded image processing technologyThe characteristics of space-based embedded image processing technology are: first, embedding, that is, high requirements for volume, weight and power consumption; second, complexity, to deal with G-level pixel frames; third, reliability, requiring poor adaptability The working environment has a long life; the fourth is real-time, and generally requires a calculation time of the second level. In order to realize these characteristics, it is necessary to study from the aspects of function, structure and physical realization of aerospace embedded computers.
(1) Unified architecture model
In order to meet the requirements of improving chip integration and shortening the design cycle, the IP core-based design platform technology and the collaborative design method from function to architecture have been developed. Because the computer architecture of non-control flow is complex and inefficient, the current computer architecture adopts the architecture of control flow. According to the classification model of computer architecture proposed by us, the architecture of control flow can be divided into three categories: The instruction flow-based architecture is based on the architecture represented by the microprocessor. According to Flynn, the two logical concepts of instruction flow and data flow are used to share the four architectures of SISD, SIMD, MISD and MIMD. The second is based on data. The architecture of the stream is an architecture represented by an ASIC (such as a Systolic array) circuit. Because it has only the concept of data stream, it has only two types of SD and MD. Since the efficiency of the ASIC circuit is high, in order to overcome the flexibility of no processor. This shortcoming has emerged as a static programmable FPGA circuit; the third is based on the ConfiguraTIon Stream architecture, usually called Reconfigurable architecture, which is a dynamic programmable circuit, shared SCSD, SCMD, MCSD, MCMD four categories.
These logically categorized architectures can be used in combination, with 1023 options. There are more solutions for specific implementations. For example, the instruction sets of processors from different vendors are different.
The collaborative design of function and architecture is completed through functional-to-architecture mapping. To ensure the efficiency and unification of this mapping, a unified architecture model is proposed to unify the architecture from three aspects. First, a Unified _ISA model is proposed. As shown in Figure 1, the above three architectures can be unified from the instruction set. Secondly, an intermediate mapping language that compromises high-level language and assembly language is proposed. It can unify the compatibility and readability of high-level languages ​​with the program efficiency and mapping directness of assembly language. Third, through the programming of intermediate mapping language, the design of soft components and hard components can be unified.
Figure 1 Logical concept diagram of the Unified _ISA model
Specifically, for the instruction stream architecture, the instruction sub-sets of the four types of architectures of SISD, SIMD, MISD, and MIMD are unified into the instruction set of the SISD architecture. The architecture of the data flow and the configuration flow is increased by corresponding The instructions are unified into the instruction set of the SISD architecture; in other words, the four MPP units of SIMD, MIMD, ASIC and RC Device in Figure 1 can be described by software components. These soft components can be executed directly on the SIMD or MIMD architecture, or they can be automatically mapped into ASIC or RC Device circuits.
(2) Virtual parallel computing array
Due to the need for G-level pixel frame remote sensing image processing, the MPP parallel computing array has been developed because the image frames are always two-dimensional, and the corresponding processing element array is also two-dimensional, as shown in FIG. Although the chip integration is already very high, it is not possible to develop an array of G processing elements of a G-level pixel frame on a single chip. Now, there are only an array of millions of processing elements completed by WSI technology. Therefore, the virtual processing element array technology can only be used to solve the convenience of the MPP program design and the readability of the program itself. In other words, the MPP image processing program is designed according to the virtual parallel computing array, that is, when designing the MPP program, it is always assumed that the values ​​of M and N of the grid array in FIG. 2 are equal to the dimension of the image frame. The actual processing element array size m&TImes;n is much smaller than M&TImes;N, and the MPP program is executed by automatically mapping to the actual processing element array. For the characteristics of image processing algorithms, image processing MPP computing arrays are usually designed according to the SIMD architecture. The corresponding design problems are: the location representation and location selection of the processing meta PE, the PIM design to solve the bandwidth problem between the image processor and the image memory, and the parallel resampling problem.
Figure 2 M&TImes; N virtual processing element array
(3) Bionic physical realization technology
The desire for the mysteries of the universe and the brain has stimulated the journey of human space and the journey of the human body, making the embedded computing technology evolve from the traditional computing model to the self-computing model to the natural computing model. The traditional implementation of chip implementation technology has now evolved from a single-function chip to a new stage of a multi-functional SoC chip. Software implementation techniques have gone from structured programming to Object-oriented programming to Component-based programming and to Agent-based Programming.
In August 1956, John McCarthy first proposed the concept of artificial intelligence (AI). At that time, he said: "The era of machine thinking will not come in 20 years." But now artificial intelligence is still in its infancy, only Success in “cognitive science†and expert systems illustrates the difficulty of artificial intelligence. It is estimated that from the 200X year to the 201X year, it will enter the 30nm nanoelectronic era. The robotic autonomous mobile operation, gravity walking and airflow pronunciation, as well as the lensing of the fisheye lens will be more perfect. The biomimetic implementation technology of autonomic computing is mainly based on the inference ability of fuzzy logic, the learning ability of neural network and the optimization ability of genetic computing. The real challenge is to change and redefine the nature of computing hardware.
In many ways, the human body is the most effective computer. The nervous system in the human body is caused by the movement of Na Sodium ions and potassium (K, Potassium) ions, transmitting signals between the brain and the nerve centers all over the body. It is interpreted and processed by the brain to govern human activities. It is estimated that from 201X to 20XX, it will enter the 10nm nanoelectronic era, promoting the development of quantum computing self-assembly technology, chemical computing DNA technology and fault-tolerant computational neuron technology. In particular, molecular self-assembly technology has achieved practical results such as laboratory chips (ALM).
ConclusionIn summary, we propose a unified architecture model from the function, from the structure will design a processing element array that can effectively support the virtual parallel computing program design, from the physical implementation will study a kind of support Design platform for assembly technology. In short, SoC chips, nano-manufacturing and self-installation technologies will further promote the development of embedded image processing technology in the space age.
Dongguan Tuojun Electronic Technology Co., Ltd , https://www.fibercablessupplier.com