Verilog HDL is a hardware description language for modeling digital systems from a variety of abstract design levels, from algorithm level to gate level to switch level. The complexity of the digital system objects being modeled can range between simple gates and complete electronic digital systems. Digital systems can be described hierarchically and can be explicitly modeled in the same description.
The Verilog HDL language has the following description capabilities: behavioral characteristics of the design, data flow characteristics of the design, structural composition of the design, and delay and waveform generation mechanisms including response monitoring and design verification. All of these use the same modeling language. In addition, the Verilog HDL language provides a programming language interface that allows you to access the design from outside the design during simulation and verification, including the specific control and operation of the simulation.
The Verilog HDL language not only defines the grammar, but also defines clear simulation and simulation semantics for each grammatical structure. Therefore, models written in this language can be verified using the Verilog simulator. Languages ​​inherit a variety of operators and structures from the C programming language. Verilog HDL provides extended modeling capabilities, many of which were initially difficult to understand. However, the core subset of the Verilog HDL language is very easy to learn and use, which is sufficient for most modeling applications. Of course, a complete hardware description language is sufficient to describe from the most complex chips to complete electronic systems.
The Verilog HDL language was originally developed in 1983 by Gateway Design AutomaTIon for its hardware modeling language for its simulator products. At the time it was just a special language. Due to the widespread use of their analog and emulator products, Verilog HDL is gaining acceptance among many designers as an easy to use and practical language. In an effort to increase language popularity, the Verilog HDL language was introduced to the public in 1990. Open Verilog InternaTIonal (OVI) is an international organization that promotes the development of Verilog. In 1992, OVI decided to promote the Verilog OVI standard to become an IEEE standard. This effort was finally successful, and the Verilog language became an IEEE standard in 1995, called IEEE Std 1364-1995. The complete standard is described in detail in the Verilog Hardware Description Language Reference Manual.
Main ability
Listed below are the main capabilities of the Verilog hardware description language:
* Basic logic gates such as and, or, and nand are built into the language.
* Flexibility in user-defined primitive (UDP) creation. User-defined primitives can be either combinatorial logic primitives or sequential logic primitives.
* Switch-level basic structural models such as pmos and nmos are also built into the language.
* Provide explicit language structure to specify port-to-port delay and path delay and design timing checking in the design.
* Models can be modeled in three different ways or in a mixture. These include: behavioral descriptions—using procedural structural modeling; data flow methods—modeling using continuous assignment statements; structured approach—using gate and module instance statements to describe modeling.
* There are two types of data types in Verilog HDL: wire network data types and register data types. The wire mesh type represents the physical connection between components, while the register type represents an abstract data storage component.
* Ability to describe hierarchical designs, which can be described using a module instance structure.
* The size of the design can be arbitrary; the language does not impose any restrictions on the size (size) of the design.
* Verilog HDL is no longer the proprietary language of some companies but the IEEE standard.
* The Verilog language is accessible to both humans and machines, so it serves as an interactive language between EDA tools and designers.
* The Verilog HDL language description capability can be further extended by using the Programming Language Interface (PLI) mechanism. PLI is a collection of routines that allow external functions to access information within the Verilog module, allowing the designer to interact with the simulator.
* Design can be described at multiple levels, from switch level, gate level, register transfer level (RTL) to algorithm level, including process and queue levels.
* Ability to fully model the design at the switch level using built-in switch-level primitives.
* The same language can be used to generate simulation incentives and validation constraints for specified tests, such as the assignment of input values.
* Verilog HDL is able to monitor the execution of analog verification, ie the values ​​designed during the simulation verification process can be monitored and displayed. These values ​​can also be used to compare with expected values, and in the event of a mismatch, print a report message.
* In the behavioral level description, Verilog HDL can not only design descriptions at the RTL level, but also design descriptions at the architecture level and its algorithm level behavior.
* Ability to perform structural descriptions at the structural level using gate and module instantiation statements.
* Verilog HDL's hybrid approach modeling capability, in which each module can be modeled at different design levels.
* Verilog HDL also has built-in logic functions such as & (bitwise AND) and | (bitwise OR).
* Can be used in languages ​​for high-level programming language constructs such as conditional statements, situational statements, and looping statements.
* Concurrency and timing can be modeled explicitly.
* Provide strong file literacy.
* Language is non-deterministic in certain situations, ie models can produce different results on different simulators; for example, the sequence of events on the event queue is not defined in the standard.
exercise
1. In what year was Verilog HDL standardized for the first time by the IEEE?
2. Which three basic descriptions does Verilog HDL support?
3. Can I describe the timing of a design using Verilog HDL?
4. What features in the language can be used to describe parametric design?
5. Can I write a test validator using Verilog HDL?
6. Which company was the first to develop Verilog HDL?
7. What are the two main types of data in Verilog HDL?
8. What does UDP stand for?
9. Write the names of the two switch-level basic gates.
10. Write the names of the two basic logic gates.
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