uC/GUI is a graphics user interface (GUI) software package for embedded systems introduced by MITRIMM. Since uC/GUI is written entirely in ANSI-C, it is processor-independent and can be easily ported. It can be used on different operating systems and embedded microprocessors, and can support different sizes of graphic liquid crystal displays. It is hierarchically designed, powerful, and portable, and is widely used in embedded applications such as PDAs, set-top boxes, and DVD NCD players. This article details the migration of uC/GUI in the ARM kernel S3C44B0X. Practice has proved that uC/GUI has good real-time and stability and a wide application prospect.
1, hardware connection and liquid crystal display principleThe hardware used in this design uses the ARM7 development board, and the LCD module is the L78C64. It is a 7.8in 256-color STN LCD display with a resolution of 640 & TImes; 480.
The definition of the external interface signal of the LCD controller and its correspondence with the signals of the LCD module are as follows:
(1) VFRAME: Frame synchronization signal between the LCD controller and the LCD driver. This signal is responsible for indicating the start of a new frame of the LCD screen. The LCD controller inserts a VFRAME signal as soon as a full frame display is completed and begins the display of a new frame. The signal corresponds to the YD signal of the LCD module;
(2) VLINE: Line sync pulse signal between the LCD controller and the LCD driver. This signal is used to transfer the contents of the LCD driver horizontal line (row) shift register to the LCD screen display. The LCD controller inserts a VLINE signal after the entire horizontal line (full line) of data is moved into the LCD controller. The signal corresponds to the LP signal of the LCD module;
(3) VCLK: pixel clock signal between the LCD controller and the LCD driver. The data sent by the LCD controller is sent out at the rising edge of VCLK and sampled by the LCD driver on the falling edge of VCLK. The signal corresponds to the XCK signal of the LCD module;
(4) VM: AC signal of the LCD driver. The VM signal is used by the LCD driver to change the polarity of the voltages of the rows and columns, thereby controlling the display and extinction of the pixel points. The VM signal can be synchronized with each frame or with a variable number of VLINE signals;
(5) VD3~0 LCD: Data input port of pixel. Corresponds to D3~0 of LCD module:
(6) VD7~4 LCD: Data input port of pixel. Corresponds to D7~4 of the LCD module.
Liquid crystal display principle: The data written on the entire screen is called 1 "frame" data, and YD is the frame synchronization signal, which starts a new frame of data on the LCD screen. The length of time between two YD pulses is called the frame period. According to the characteristics of the LCD module, the refresh time is 12 to 14 ms, and the frequency is 70 to 80 Hz. Each frame includes 480 LP pulses. LP is a row (a total of 480 lines) of data input latch signals, that is, a line sync pulse signal. This signal initiates a new line of data on the LCD screen. XCK is a line data input signal, that is, a clock signal for data transmission of pixel points in one line. Each set of 8-bit data is input latched on the falling edge of XCK, so every 1 line includes 640 & TImes; 3 / 8 XCK pulse signals. D0 to D7 are 8-bit display data input signals.
2, driver designThe initialization of the liquid crystal is completed in three steps.
(1) Initialization of the I/O port
Since the PC interface and the PD interface of the S3C44B0X are used as the LCD drive interface, it is necessary to set the PC interface to operate in the third functional state and the PD interface to operate in the second functional state.
(2) Setting method of corresponding control register
The S3C44B0X includes an LCD controller timing generator, TIMEGEN, which generates VFRAM, VLINE, VCLK and VM control timing. These control signals are configured by registers LCOCON1 and LCDCON2. By setting the register configuration items, TIMEGEN can generate control signals suitable for various LCD screens.
The VFRAM and VLINE pulses are generated by configuring the HOZVAL and LINEVAL of the LCDCON2 register. Each field is related to the size and display mode of the LCD.
Among them, HOZVAL = (display width / VD data line digits) -1.
In color mode, the display width = 3 × the number of pixels per line.
For the selected liquid crystal module, HOZVAL=(640×3/8)-1; LINEVAL=(display width)-1.
For the selected LCD module, LlNEVAL=480-1.
The frequency of the VCLK signal can be determined by the CLKVAL field of the LCDCON1 register, ie
VCLK=MCLK/(CLKVAL×2)
The LCD controller has a maximum VCLK frequency of 16.5MHz and supports almost all existing LCD drivers. Due to the above relationship, the value of CLKVAL determines the frequency of VCLK. To determine the value of CLKVAL, the rate at which the LCD controller transfers data to the VD port should be calculated so that the value of VCLK is greater than the rate of data transfer.
The formula for the data transfer rate is:
Data transmission rate = HS × VS × FR × MV
Among them, HS-LCD row pixel value; VS-LCD column pixel value: FR-frame rate; MV-mode value, here take 8-bit single scan, color.
For the selected liquid crystal module: HS = 640; VS = 480; FR = 70 Hz: MV = 3/8. Therefore, the data transmission rate = 640 × 480 × 70 × 3 / 8 = 8, 064,000 Hz.
The VCLK value should be greater than 8MHz and less than 16MHz, so CLKVAL can take 9-15.
(3) Complete LCD initialization procedure
C program
Void LCD_Init_Controler()
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