Abstract: This application note introduces the soft-start method (SSP) used by the DS3994 4-channel cold cathode fluorescent lamp (CCFL) controller. It can gradually increase the duty cycle of the MOSFET at the beginning of each lamp. This article explains how to modify the default SSP value of the device to meet the ramp time required in the application.
Overview DS3994 is a 4-channel cold cathode fluorescent lamp (CCFL) controller that can be used for liquid crystal display (LCD) backlight. When burst dimming is used to adjust the brightness of the lamp, the DS3994 uses soft start to reduce the audio transformer noise each time the lamp is lit. The soft start characteristic (SSP) of DS3994 is controlled by four soft start characteristic registers (SSP1 / 2/3/4). The SSP register is programmed at the factory, and the default value is suitable for most applications. However, the user can modify the value of the SSP register through the I²C interface to obtain a customized SSP value. This application note describes how to make adjustments.
DPWM soft start DS3994 uses digital pulse width adjustment (DPWM) signal (22.5Hz to 440Hz) to achieve efficient and accurate lamp brightness adjustment. During the high level of PWM, CCFL is turned on and working at the lamp frequency. This period is called the "burst" cycle. During the low level of PWM, CCFL is turned off and no current flows. By adjusting the duty cycle of the PWM pulse, the brightness of the CCFL can be increased or decreased.
At the beginning of each lamp, the DS3394 provides a soft start, slowly increasing (ie, ramping up) the duty cycle of the MOSFET gate drive. This ramp reduces the audio transformer noise that may be generated due to current surges on the primary side of the transformer. The soft start ramp characteristics are controlled by 4 SSP registers (SSP1 / 2/3/4). The SSP register can be programmed to implement eight different MOSFET gate duty cycles. Each programming cycle is repeated twice, for a total of 16 lamp cycles. Although the soft start length is fixed at 16 lamp cycles, the soft start method is programmable and can be adjusted for the application.
The default value of the SSP register When setting the soft-start ramp characteristics of the DS3994, there are a total of 8 driver duty cycles to choose from. Each of the four SSP registers (SSP1 / 2/3/4) has two 4-bit codes to determine the MOSFET duty cycle (MDC) of two lamp cycles at the beginning of each DPWM burst. Table 1 shows the duty cycle of the corresponding code. The soft start gate period is based on the most recent lamp duty cycle.
Table 1. Available MOSFET duty cycle (MDC)
Table 2 shows the address and default value of the SSP register.
Table 2. SSP register addresses and default values
Modifying the soft-start characteristics During soft-start, the SSP register determines the duty cycle (MDC) of 16 MOSFETs to ensure that these MDCs gradually rise from 0 to their most recent value (or nominal value). The time when MDC rises is called the ramp time. The ramp time can be set from 0 to 16 lamp cycles in steps of two lamp cycles. The shorter the ramp time, the steeper the slope of the current envelope.
Table 3 gives the recommended values ​​of the SSP register for different ramp times. The user can select the appropriate SSP register value to complete the required ramp time. The default value of the DS3994 SSP is 12 ramp cycles.
Table 3. Recommended values ​​of SSP registers for different ramp times
The software of DS3994 can be used to program the SSP register. The software can be downloaded from. The software interface is shown in Figure 1. Users can use the Byte Read / Write section to adjust the SSP register value.
Figure 1. DS3994 software interface for user programming SSP registers
Figures 2, 3 and 4 show the CCFL current waveforms measured under different ramp cycles during the soft start using the register values ​​recommended in Table 3. The SSP shown in Figure 3 has 12 ramp cycles, and the DS3994 takes the default setting. Figures 2 and 4 correspond to the case where the SSP has 8 and 16 ramp cycles, respectively.
Figure 2. Lamp current waveform, 8 SSP ramp periods
Figure 3. Lamp current waveform, 12 SSP ramp periods
Figure 4. Lamp current waveform, 16 SSP ramp periods
Overview DS3994 is a 4-channel cold cathode fluorescent lamp (CCFL) controller that can be used for liquid crystal display (LCD) backlight. When burst dimming is used to adjust the brightness of the lamp, the DS3994 uses soft start to reduce the audio transformer noise each time the lamp is lit. The soft start characteristic (SSP) of DS3994 is controlled by four soft start characteristic registers (SSP1 / 2/3/4). The SSP register is programmed at the factory, and the default value is suitable for most applications. However, the user can modify the value of the SSP register through the I²C interface to obtain a customized SSP value. This application note describes how to make adjustments.
DPWM soft start DS3994 uses digital pulse width adjustment (DPWM) signal (22.5Hz to 440Hz) to achieve efficient and accurate lamp brightness adjustment. During the high level of PWM, CCFL is turned on and working at the lamp frequency. This period is called the "burst" cycle. During the low level of PWM, CCFL is turned off and no current flows. By adjusting the duty cycle of the PWM pulse, the brightness of the CCFL can be increased or decreased.
At the beginning of each lamp, the DS3394 provides a soft start, slowly increasing (ie, ramping up) the duty cycle of the MOSFET gate drive. This ramp reduces the audio transformer noise that may be generated due to current surges on the primary side of the transformer. The soft start ramp characteristics are controlled by 4 SSP registers (SSP1 / 2/3/4). The SSP register can be programmed to implement eight different MOSFET gate duty cycles. Each programming cycle is repeated twice, for a total of 16 lamp cycles. Although the soft start length is fixed at 16 lamp cycles, the soft start method is programmable and can be adjusted for the application.
The default value of the SSP register When setting the soft-start ramp characteristics of the DS3994, there are a total of 8 driver duty cycles to choose from. Each of the four SSP registers (SSP1 / 2/3/4) has two 4-bit codes to determine the MOSFET duty cycle (MDC) of two lamp cycles at the beginning of each DPWM burst. Table 1 shows the duty cycle of the corresponding code. The soft start gate period is based on the most recent lamp duty cycle.
Table 1. Available MOSFET duty cycle (MDC)
| MDC Code | MOSFET Duty Cycle—Percentage of the Most Recent Control Value (%) |
| 0h | 0 |
| 1h | 25 |
| 2h | 37.5 |
| 3h | 50 |
| 4h | 62.5 |
| 5h | 75 |
| 6h | 87.5 |
| 7h | 100 |
| 8h-Fh | Reserved |
Table 2 shows the address and default value of the SSP register.
Table 2. SSP register addresses and default values
| SSP # | Address | Default | MSB | LSB | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
| SSP1 | F0h | 21h | Lamp Cycles 3 and 4 | Lamp Cycles 1 and 2 | ||||||
| SSP2 | F1h | 43h | Lamp Cycles 7 and 8 | Lamp Cycles 5 and 6 | ||||||
| SSP3 | F2h | 65h | Lamp Cycles 11 and 12 | Lamp Cycles 9 and 10 | ||||||
| SSP4 | F3h | 77h | Lamp Cycles 15 and 16 | Lamp Cycles 13 and 14 | ||||||
Modifying the soft-start characteristics During soft-start, the SSP register determines the duty cycle (MDC) of 16 MOSFETs to ensure that these MDCs gradually rise from 0 to their most recent value (or nominal value). The time when MDC rises is called the ramp time. The ramp time can be set from 0 to 16 lamp cycles in steps of two lamp cycles. The shorter the ramp time, the steeper the slope of the current envelope.
Table 3 gives the recommended values ​​of the SSP register for different ramp times. The user can select the appropriate SSP register value to complete the required ramp time. The default value of the DS3994 SSP is 12 ramp cycles.
Table 3. Recommended values ​​of SSP registers for different ramp times
| Number of Ramping Cycles | SSP Register Values | |||
| SSP1 (F0h) | SSP2 (F1h) | SSP3 (F2h) | SSP4 (F3h) | |
| 0 | 77h | 77h | 77h | 77h |
| 2 | 73h | 77h | 77h | 77h |
| 4 | 42h | 77h | 77h | 77h |
| 6 | 31h | 75h | 77h | 77h |
| 8 | 21h | 54h | 77h | 77h |
| 10 | 21h | 43h | 76h | 77h |
| 12 | 21h | 43h | 65h | 77h |
| 14 | 11h | 32h | 54h | 76h |
| 16 | 11h | 32h | 43h | 65h |
The software of DS3994 can be used to program the SSP register. The software can be downloaded from. The software interface is shown in Figure 1. Users can use the Byte Read / Write section to adjust the SSP register value.
Figure 1. DS3994 software interface for user programming SSP registers
Figures 2, 3 and 4 show the CCFL current waveforms measured under different ramp cycles during the soft start using the register values ​​recommended in Table 3. The SSP shown in Figure 3 has 12 ramp cycles, and the DS3994 takes the default setting. Figures 2 and 4 correspond to the case where the SSP has 8 and 16 ramp cycles, respectively.
Figure 2. Lamp current waveform, 8 SSP ramp periods
Figure 3. Lamp current waveform, 12 SSP ramp periods
Figure 4. Lamp current waveform, 16 SSP ramp periods
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